1. Field of the Invention
The present invention relates to a successive approximation register (SAR) analog-to-digital converter (ADC), and more particularly, to a SAR ADC having amplification functions.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a conventional circuit 100 for image processing. As shown in FIG. 1, the circuit 100 includes two buffers 102 and 104, a programmable gain amplifier (PGA) 100, an analog-to-digital converter (ADC) 120 and a digital signal processor (DSP) 130. In the operations of the circuit 100, the PGA 110 receives the buffered input signals Vp and Vn to generate amplified input signals, and the ADC 120 performs an analog-to-digital conversion upon the amplified input signals to generate digital input signals to the DSP 130, where a gain of the PGA 110 is controlled by the DSP 130.
The PGA 110 within the circuit 100 is usually implemented by a switched capacitor amplifier or a continuous-time amplifier. However, because designs of these amplifiers require higher accuracy and operations of these amplifiers require great power, the total cost of the circuit 100 is increased.